1. Field of Disclosure
The technology disclosed improves on U.S. Pat. No. 7,685,545, which is hereby incorporated by reference. The new technology involves renaming at least some cells in a hierarchical design of a circuit so that functionally identical cells have matching names. New cell names, after renaming, are propagated upward through at least some levels of the design hierarchy. Optionally, cells that appear to be derivative or based on small changes also can be given matching names.
2. Prior Disclosure and New Opportunity
The '545 patent describes the advantages of identifying and comparing chip design intellectual property using digests of design data rather than the design data itself. The technology disclosed made it possible to identify, for example, altered copies of intellectual property within a large chip design file in a polygon-based layout format such as GDSII or OASIS without flattening the design and generating hundreds of gigabytes of polygon data. In particular, that patent showed how to identify copies of design units (also known as cells) using digests even when their names change.
The technology disclosed in the '545 patent detects changes in names of cells embedded within other cells and makes it practical to identify and focus on such changes. However, the '545 patent did not fully address sources of noise in reporting changes that relate to production scale designs. By noise, we mean reports of changes that do not assist a designer in understanding the scope and impact of functional design changes.
In practice, typical design files contain many thousands of cells, and there are many duplicate cells. Even hierarchical cells may be duplicated, and cell names may be changed at all levels of the design hierarchy. These non-functional changes introduce noise into the analysis process. An opportunity arises to further define and discriminate among changes that are detected.